1. Field of the Invention
The invention pertains generally to semiconductor devices and, more particularly, to semiconductor-on-insulator devices.
2. Art Background
Semiconductor-on-insulator (SOI) devices are semiconductor devices which are formed on an electrically insulating region of a substrate. Such a region includes, for example, a layer of insulating material (material having a bandgap greater than about 3 eV), e.g., a layer of SiO.sub.2, overlying semiconductor material such as silicon.
SOI devices offer several advantages over conventional semiconductor devices. For example, SOI devices offer the possibility of lower parasitic capacitances, and thus faster switching times. In addition, the undesirable phenomenon of latchup (regarding latchup, see, e.g., S. M. Sze, ed., VLSI Technology, McGraw Hill, New York, 1983, page 481), often exhibited by conventional CMOS (complementary metal-oxide-semiconductor) devices, is avoided by CMOS devices in an SOI configuration. SOI devices are also less susceptible to the adverse effects of ionizing radiation and thus are more reliable. Further, the possibility of achieving relatively high speed integrated circuits without using relatively small-dimension design rules, through the fabrication of multi-level integrated circuits, i.e., circuits where one layer of devices is fabricated on top of, and electrically connected to, an underlying layer of devices, is also offered by SOI technology.
While these advantageous properties of SOI devices result from the vertical dielectric isolation, this isolation also produces difficulties not encountered with conventional devices. In conventional devices, electrical interactions between the device substrate and the device active region, e.g., the current channel of a MOSFET (metal-oxide-semiconductor field effect transistor), are advantageously utilized. For example, accumulated charge in the device active region alters the device threshold voltage (the voltage at which, for example, the current channel of an enhancement-mode MOSFET begins to conduct current). However, this accumulated charge is readily removed through the substrate by applying an appropriate backgate bias, i.e., a voltage applied to the substrate which attracts the accumulated charge away from the active layer, into the substrate, and out through a conductive lead. For example, a negative voltage applied to the substrate attracts holes from the active layer into the substrate, while a positive voltage attracts electrons. Alternatively, it is possible to change the threshold voltage of a device, if desired, by applying a back-gate bias through the substrate to the active region.
In contrast, in an SOI device, the insulating region prevents both the conduction of charge from the active region into the substrate, and the application of a potential through the substrate to the active region. Thus, this lack of flexibility due to the SOI insulating region is often quite inconvenient. For example, during operation of an n-channel SOI MOSFET, holes continue to accumulate in the active layer of the device, between the source and drain, until the concomitant electric potential increases sufficiently to produce a shift in the threshold voltage of the device, with a resulting sudden increase, i.e., a kink, in the current conducted by the device. This "kink" introduces errors into the information being processed by the device.
The kink effect and threshold voltage have been controlled in both conventional and SOI devices by applying an appropriate voltage (a voltage which attracts kink-producing charge carriers) to a low resistance diffusion contact formed in the active layer(s) of a device. Often, to withdraw kink-producing charges, a conventional CMOS device includes a low resistance contact to one of the two types (n-channel or p-channel) of MOSFETs of the device, which either partially or completely encircles the one type of MOSFETs. However, the use of such contacts in any device, including an SOI device, is undesirable because the contacts occupy an excessive region of the substrate.
SOI fabrication techniques, such as the lateral seeding process, although advantageous, also present difficulties. In the lateral seeding process, as described by Lam et al, "Single Crystal Silicon-on-Oxide by a Scanning CW Laser Induced Lateral Seeding Process," Journal of the Electrochemical Society, 128, 1981 (1981), a scanning CW laser is used to propagate single crystal structure from a single crystal region through an adjacent layer of polycrystalline silicon (polysilicon) deposited onto a substrate surface which includes a region of (insulating) silicon dioxide. As noted by Lam et al, supra, at page 1983, the lateral seeding process displaces the oxide regions from their original positions. If the original positions of the oxide regions had corresponded to the positions of the components of an IC, as defined by a mask set, then, as stated by Lam et al, the displacement of the oxide regions would cause severe difficulty in placing each IC component in a silicon region overlying an oxide region. This displacement problem largely precludes the use of available circuit designs and mask sets, in conjunction with the lateral seeding process (as currently practiced), for fabricating SOI ICs.
Thus, space efficient, kink-free SOI devices with easily controlled threshold voltage, as well as fabrication methods which permit the use of available circuit designs and mask sets to form SOI ICs, are an elusive goal.